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16-Bit, 80 MSPS A/D Converter AD10678
FEATURES
80 MSPS sample rate 80 dBFS signal-to-noise ratio Transformer-coupled analog input Single PECL clock source Digital outputs True binary format 3.3 V and 5 V CMOS compatible
FUNCTIONAL BLOCK DIAGRAM
AIN
AD10678
AIN ADC 14 DOUT0 14 DIGITAL POSTPROCESSING DOUT15 ADC AGND 5VA 3.3VE AGND 14 DRY CLOCK DISTRIBUTION CIRCUIT DGND 3.3V DGND OUTPUT DATA BITS
ADC
ADC
14
APPLICATIONS
Low signature radar Medical imaging Communications instrumentation Instrumentation Antenna array processing
ANALOG POWER
ENCODE ENCODE
DIGITAL POWER
Figure 1.
GENERAL DESCRIPTION
The AD10678 is a 16-bit, high performance, analog-to-digital converter for applications that demand increased SNR levels. Exceptional noise performance and a typical signal-to-noise ratio of 80 dBFS are obtained by digitally postprocessing the outputs of four ADCs. Only a single analog input and PECL sampling clock, as well as 3.3 V and 5 V power supplies, are required. The AD10678 is assembled using a 0.062" thick laminate board with three sets of connector interface pads to accommodate analog and digital isolation. Analog Devices recommends using this connector from Samtec: FSI-110-03-G-D-AD-K-TR. The overall card fits a 2.2" x 2.8" PCB specified from 0C to 70C.
PRODUCT HIGHLIGHTS
1. 2. 3. Guaranteed sample rate of 80 MSPS. Input signal conditioning with optimized noise performance. Fully tested and guaranteed performance.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2003 Analog Devices, Inc. All rights reserved.
03376-A-001
AD10678
TABLE OF CONTENTS
Features .......................................................................................... 1 Applications................................................................................... 1 Functional block diagram ........................................................... 1 General Description..................................................................... 1 Product Highlights ....................................................................... 1 Revision History ........................................................................... 2 AD10678-Specifications ................................................................. 3 DC Specifications ......................................................................... 3 Digital Specifications ................................................................... 3 AC Specifications.......................................................................... 4 Switching Specifications .............................................................. 5 Explanation of Test Levels............................................................5 Absolute Maximum Ratings ............................................................6 Operating Range............................................................................6 ESD Caution...................................................................................6 Test Circuits........................................................................................7 AD10678-Typical Performance Characteristics ........................ 10 Definition of Specifications ...................................................... 12 Thermal Considerations............................................................ 12 Theory of Operation.................................................................. 13 Outline Dimensions ....................................................................... 20 Ordering Guide .......................................................................... 20
REVISION HISTORY
12/03--Data sheet changed from REV. 0 to REV.A Updated format....................................................................Universal Changes to AC Specifications table footnotes ............................... 4 Changes to Table 1............................................................................. 3 Changes to Table 3............................................................................. 6 Changes to Figure 11....................................................................... 10 Changes to Theory of Operation................................................... 13 Changes to Ordering Guide ........................................................... 20
Rev. A | Page 2 of 20
AD10678 AD10678-SPECIFICATIONS
DC SPECIFICATIONS
Table 1. AVCC = 5 V, EVCC = 3.3 V, VDD = 3.3 V; TA = 25C, Differential Encode = 80 MSPS, CLOAD 10 pF, unless otherwise noted.
Parameter RESOLUTION Offset Error Gain Error Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error POWER SUPPLY REJECTION RATIO (PSRR) ANALOG INPUTS (AIN, AIN)1 Differential Input Voltage Range Differential Input Resistance Differential Input Capacitance Input Bandwidth VSWR 2 POWER SUPPLY 3 Supply Current IAVCC (AVCC = 5.0 V) IEVCC (EVCC = 3.3 V) IVDD (VDD = 3.3 V) Total Power Dissipation 4 Test Level I I V V V V V V V V IV V Min -0.30 -7 Typ 16 +0.12 0.7 4 13 200 60 2.15 50 2.5 0.40 1.04:1 220 Max +0.30 +7 Unit Bits %FS %FS LSB LSB ppm/C ppm/C dB V p-p nF MHz Ratio
I I I I
0.95 0.15 0.49 6.86
1.1 0.2 0.625 8.0
A A A W
1 2
Measurement includes the recommended interface connector. Input VSWR, see Figure 15. 3 Supply voltages should remain stable within 5% for normal operation. 4 Power dissipation measures with encode at rated speed and -1 dBFS analog input at 10 MHz.
DIGITAL SPECIFICATIONS
Table 2. AVCC = 5 V, EVCC = 3.3 V, VDD = 3.3 V; TA = 25C, Differential Encode = 80 MSPS, CLOAD 10 pF, unless otherwise noted.
Parameter ENCODE INPUTS (ENCODE, ENCODE) Differential Input Voltage Range Differential Input Resistance Differential Input Capacitance LOGIC OUTPUTS (D15 to D0) Logic Compatibility Logic 1 Voltage--ILOAD 100 mA Logic 0 Voltage--ILOAD 100 mA Output Coding Series Output Resistance--per Bit Test Level IV V V Min 0.4 100 160 CMOS 0.9 x VDD 0.4 True Binary 120 Typ Max Unit V p-p pF
IV IV
V V
Rev. A | Page 3 of 20
AD10678
AC SPECIFICATIONS
Table 3. AVCC = 5 V, EVCC = 3.3 V, VDD = 3.3 V; TA = 25C, Differential Encode = 80 MSPS, CLOAD 10 pF, unless otherwise noted.
Parameter SNR 1 Analog Input @ -6 dBFS Test Level 2.5 MHz 10 MHz 30 MHz 70 MHz 2.5 MHz 10 MHz 30 MHz 70 MHz 2.5 MHz 10 MHz 30 MHz 70 MHz I I I I I I I I I I I I Min 77.5 77.5 77 76 77.2 77.2 76.6 74.7 88 88 84 81 Typ 80.5 80.5 80.2 78 80.3 80.3 79.7 77.4 97.2 97.2 94.2 91.7 Max Unit dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS
SINAD 2 Analog Input @ -6 dBFS
SFDR 3 Analog Input @ -6 dBFS
TWO-TONE 4 Analog Input @ -7 dBFS--IMD f1 = 10 MHz, f2 = 12 MHz f1 = 70 MHz, f2 = 72 MHz
V V
96 84
dBFS dBFS
1
Analog input signal power at -6 dBFS; signal-to-noise (SNR) is the ratio of signal level to total noise (first five harmonics removed). Encode = 80 MSPS. SNR is reported in dBFS, related back to converter full scale. 2 Analog input signal power at -6 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 80 MSPS. SINAD is reported in dBFS, related back to converter full scale. 3 Analog input signal equals -6 dBFS; SFDR is the ratio of converter full scale to worst spur. 4 Both input tones at-7 dBFS; two tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third-order intermodulation product.
Rev. A | Page 4 of 20
AD10678
SWITCHING SPECIFICATIONS
Table 4. AVCC = 5 V, EVCC = 3.3 V, VDD = 3.3 V; TA = 25C, Differential Encode = 80 MSPS, CLOAD 10 pF, unless otherwise noted.
Parameter MAXIMUM CONVERSION RATE MINIMUM CONVERSION RATE DUTY CYCLE ENCODE INPUTS PARAMETERS Encode Period @ 80 MSPS, tENC Encode Pulse Width High @ 80 MSPS, tENCH Encode Pulse Width Low @ 80 MSPS, tENCL ENCODE/DATA (D15:D0) Propagation Delay, tPDH Valid Time, tPDL ENCODE/DATA READY1 Encode Rising to Data Ready Falling, tDR_F Encode Rising to Data Ready Rising, tDR_R DATA READY/DATA1 Data Ready to Data (Hold Time)--tH_DR Data Ready to Data (Setup Time)--tS_DR APERTURE DELAY, tA APERTURE UNCERTAINTY (JITTER), tJ PIPELINE DELAYS Test Level I IV IV V V V Min 80 40 12.5 6.25 6.25 6.7 7.3 12.6 6.4 10 1 480 500 10 Typ Max 30 60 Unit MSPS MSPS % ns ns ns ns ns ns ns ns ns ps fs rms Cycles
V V V
1
Duty Cycle = 50%.
EXPLANATION OF TEST LEVELS
I. II. III. IV. V. VI. 100% production tested. 100% production tested at 25C and sample tested at specified temperatures. Sample tested only. Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. 100% production tested at 25C; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices.
Rev. A | Page 5 of 20
AD10678 ABSOLUTE MAXIMUM RATINGS
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 5. AD10678 Stress Ratings
Parameter AVCC to AGND EVCC to AGND VDD to DGND Analog Input Voltage Analog Input Current Encode Input Voltage Digital Output Voltage Maximum Junction Temperature Storage Temperature Range Ambient Maximum Operating Temperature Ambient Rating 0 V to 7 V 0 V to 6 V -0.5 V to +3.8 V 0 V to AVCC 25 mA 0 V to 5 V -0.5 V to VDD 150C -65C to +150C 92C
OPERATING RANGE
Operating Ambient Temperature Range: 0C to 70C. See Thermal Considerations section. Table 6. Output Coding (True Binary)
Code 65535 . . . 32768 32767 . . . 0 AIN (V) +1.1 . . . 0 -0.000034 . . . -1.1 Digital Output 1111 1111 1111 1111 . . . 1000 0000 0000 0000 0111 1111 1111 1111 . . . 0000 0000 0000 0000
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. A | Page 6 of 20
AD10678 TEST CIRCUITS
tA
N N+1 N+2 N+3 N+4 N+5 N+6
ANALOG INPUT
tENC
ENCODE, ENCODE N N+1
tENCL
tENCH
N+2 N+3 N+4 N+5 N+6
tPDH
DATA BITS, D[15:0] N-10 N-9
tPDL
N-8 N-7 N-6 N-5
tS_DR
DATA-READY OUTPUT N N+1 N+2
tH_DR
N+3
tDR_R
N+4
tDR_F
N+5 N+6
03376-A-002
Figure 2. Timing Diagram
VCH AVCC
BUF AIN 200 AIN 1:1 25 500 VCH 25 x4 AVCC 500 BUF VCL 500 BUF
T/H
VREF
T/H
03376-A-003
VCL
Figure 3. Analog Input Stage
EVCC 37.5k ENC
03376-A-004
VDD
VDD P
100 ENC PECL DRIVER
N
Figure 4. Equivalent Encode Input
VDD VDD P
03376-A-023
Figure 5. Digital Output Stage
MACROCELL LOGIC N
DRY 1k
Figure 6. Data-Ready Output
Rev. A | Page 7 of 20
03376-A-005
MACROCELL LOGIC
120
D0-D15
AD10678
Table 7. Interfaces 1 and 2: Digital Pin Function Descriptions
P1: Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Mnemonic DGND DGND DOUT15 NC DOUT14 DGND DOUT13 NC DOUT12 DGND DOUT11 NC DOUT10 DGND DOUT9 NC DOUT8 DGND DGND DRY Function Digital Ground Digital Ground Data Bit Output No Connection Data Bit Output Digital Ground Data Bit Output No Connection Data Bit Output Digital Ground Data Bit Output No Connection Data Bit Output Digital Ground Data Bit Output No Connection Data Bit Output Digital Ground Digital Ground Data Ready Output P2: Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Mnemonic DGND DGND +3.3VD DOUT0 +3.3VD DOUT1 +3.3VD DOUT2 DGND DOUT3 DGND DOUT4 DGND DOUT5 DGND DOUT6 +3.3VD DOUT7 +3.3VD DGND Function Digital Ground Digital Ground Digital Voltage (VDD) Data Bit Output Digital Voltage (VDD) Data Bit Output Digital Voltage (VDD) Data Bit Output Digital Ground Data Bit Output Digital Ground Data Bit Output Digital Ground Data Bit Output Digital Ground Data Bit Output Digital Voltage (VDD) Data Bit Output Digital Voltage (VDD) Digital Ground
Table 8 Interface 3: Analog Pin Function Descriptions
P3: Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Mnemonic +3.3VE +5.0VA +3.3VE +5.0VA AGND +5.0VA AGND +5.0VA AGND AGND AGND AIN AGND AIN ENCODE AGND ENCODE AGND AGND AGND Function Encode Voltage (EVCC) Analog Voltage (AVCC) Encode Voltage (EVCC) Analog Voltage (AVCC) Analog Ground Analog Voltage (AVCC) Analog Ground Analog Voltage (AVCC) Analog Ground Analog Ground Analog Ground Analog Input Analog Ground Analog Input Encode Input Analog Ground Encode Input Analog Ground Analog Ground Analog Ground
Rev. A | Page 8 of 20
AD10678
Top View of Interface PCB Assembly Dimensions shown in inches Tolerances: 0.xx = 10 mils 0.xxx = 5 mils
0.466
20
2 P2
MH4
19 0.960
1
0.888 P3 19 20 MH2 2.148
1.223 1.693 0.433
1
2 0.925
0.805 MH1 0.526 MH3 0.900 20 2 P1
19 0.955 0.757
1
INTERFACE NOTES: SUGGESTED INTERFACE MANUFACTURER: SAMTEC INTERFACE PART NUMBERS FOR P1-P3: FSI-110-03-G-D-AD-K-TR (20-PIN) HOLES 1-4 ACCOMMODATE 2-56 THREADED HARDWARE. USE FOUR 2-56 NUTS FOR SECURING THE PART TO INTERFACE PCB. MANUFACTURER: BUILDING FASTENERS PART NUMBER: HNSS256 DIGIKEY #: H723-ND
Figure 7. Header Interface Dimensions (Inches)
Rev. A | Page 9 of 20
03376-A-006
AD10678 AD10678-TYPICAL PERFORMANCE CHARACTERISTICS
0 -10 -20 -30 -40 -50
dBFS dBFS
0 ENCODE = 80MSPS AIN = 2.5MHz SNR = 80.79dBFS SFDR = 97.22dBFS -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120
03376-A-007 03376-A-010 03376-A-012 03376-A-011
ENCODE = 80MSPS AIN = 70MHz SNR = 78.31dBFS SFDR = 87.64dBFS
-60 -70 -80 -90 -100 -110 -120 -130 0 5 10 15 20 25 FREQUENCY (MHz) 30 35 40
-130 0 5 10 15 20 25 FREQUENCY (MHz) 30 35 40
Figure. 8. Single-Tone at 2.5 MHz
0 -10 -20 -30 -40 -50
dBFS dBFS
Figure 11. Single-Tone at 70 MHz
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120
03376-A-008
ENCODE = 80MSPS AIN = 10MHz SNR = 80.76dBFS SFDR = 94.81dBFS
ENCODE = 80MSPS AIN = 10.1MHz AND 12.1MHz IMD = 98.25dBFS
-60 -70 -80 -90 -100 -110 -120 -130 0 5 10 15 20 25 FREQUENCY (MHz) 30 35 40
-130 0 5 10 15 20 25 FREQUENCY (MHz) 30 35 40
Figure 9. Single-Tone at 10 MHz
0 ENCODE = 80MSPS -10 AIN = 32MHz -20 SNR = 80.18dBFS SFDR = 91.8dBFS -30 -40 -50
dBFS dBFS
Figure 12. Two-Tone at 10.1 MHz and 12.1 MHz
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120
03376-A-009
ENCODE = 80MSPS AIN = 70MHz AND 72MHz IMD = 87.5dBFS
-60 -70 -80 -90 -100 -110 -120 -130 0 5 10 15 20 25 FREQUENCY (MHz) 30 35 40
-130 0 5 10 15 20 25 FREQUENCY (MHz) 30 35 40
Figure 10. Single-Tone at 32 MHz
Figure 13. Two-Tone at 70 MHz and 72 MHz
Rev. A | Page 10 of 20
AD10678
0 -0.30 -0.60 -0.90 -1.20
dBFS dBc
100 AIN = -1dB 90 80 70 SFDR 30MHz 60 SFDR 70MHz SNR 70MHz SNR 30MHz 50 40 30 20 10
03376-A-013
SNR 2.5MHz SNR 10MHz SFDR 2.5MHz
-1.50 -1.80 -2.10 -2.40 -2.70 -3.00 1.0
SFDR 10MHz
03376-A-015 03376-A-024
15.9
30.8
45.7
60.6 75.5 90.4 105.3 120.2 135.1 150.0 FREQUENCY (MHz)
0 -80
-70
-60 -50 -40 -30 -20 FUNDAMENTAL LEVEL (dBFS)
-10
0
Figure 14. Gain Flatness
2.0 1.9 1.8 94 1.7 1.6
VSWR dBc
Figure 16. SFDR and SNR vs. Analog Input Level
100
SFDR
1.5 1.4 1.3
88
82 1.2 1.1 1.0 0.1
VSWR
03376-A-014
SNR
76 0 10 20 30 40 50 60 ANALOG INPUT FREQUENCY (MHz) 70
1
10 FREQUENCY (MHz)
100
1k
Figure 15. Analog Input VSWR
Figure 17. SFDR and SNR vs. Analog Input Frequency
Rev. A | Page 11 of 20
AD10678
DEFINITION OF SPECIFICATIONS
Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between the 50% point on the rising edge of the ENCODE command and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Differential Nonlinearity The deviation of any code from an ideal 1 LSB step. Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a "best straight line" determined by a least square curve fit. Encode Pulse Width/Duty Cycle Pulse width high is the minimum amount of time that the ENCODE pulse should be left in Logic 1 state to achieve rated performance; pulse width low is the minimum time that the ENCODE pulse should be left in low state. At a given clock rate, these specifications define an acceptable encode duty cycle. Harmonic Distortion The ratio of the rms signal amplitude to the rms value of the worst harmonic component. Minimum Conversion Rate The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Maximum Conversion Rate The encode rate at which parametric testing is performed. Output Propagation Delay The delay between the 50% point of the rising edge of the ENCODE command and the time when all output data bits are within valid logic levels. Power Supply Rejection Ratio The ratio of a change in output offset voltage to a change in power supply voltage. Signal-to-Noise-and-Distortion (SINAD) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, including the first five harmonics and dc. May be reported in dBc (i.e., degrades as signal level is lowered) or in dBFS (always related back to converter full scale).
TEMPERATURE (CASE) (C)
Signal-to-Noise Ratio (SNR) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. May be reported in dBc (i.e., degrades as signal level is lowered) or in dBFS (always related back to converter full scale). Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc (i.e., degrades as signal level is lowered) or in dBFS (always related back to converter full scale). Two-Tone Intermodulation Distortion Rejection (IMD) Ratio of the rms value of either input tone to the rms value of the worst third-order intermodulation product; reported in dBc. Voltage Standing-Wave Ratio (VSWR) The ratio of the amplitude of the elective field at a voltage maximum to that at an adjacent voltage minimum.
THERMAL CONSIDERATIONS
Due to the high power nature of the part, it is critical that the following thermal conditions be met for the part to perform to data sheet specifications. This also ensures that the maximum junction temperature (150C) is not exceeded. * * Operation temperature (tA) must be within 0C to 70C. All mounting standoffs should be fastened to the interface PCB assembly with 2-56 nuts. This ensures good thermal paths as well as excellent ground points. The unit rises to ~72C (tC) on the heat sink in still air (0 linear feet per minute (LFM)). The minimum recommended air flow is 100 linear feet per minute (LFM) in either direction across the heat sink (see Figure 18).
75 70 65 60 55 50 45 40 35 30 0 50 100 150 200 AIR FLOW (LFM) 250 300
03376-A-025
*
Figure 18. Temperature (Case) vs. Air Flow (Ambient)
Rev. A | Page 12 of 20
AD10678
THEORY OF OPERATION
The AD10678 employs four parallel, high speed analog-to-digital converters in a correlation technique to improve the dynamic range of the ADCs. The technique consists of summing the parallel outputs of the four converters to reduce the uncorrelated noise introduced by the individual converters. Signals processed through the high speed adder are correlated and summed coherently. Noise is not correlated and sums on an rms basis. The four high speed, analog-to-digital converters employ a threestage subrange architecture. The AD10678 provides complementary analog input pins, AIN and AIN . Each analog input is centered around 2.4 V and should swing 0.55 V around
Analog and Digital Power Supplies
Care must be taken when selecting a power source. Linear supplies are recommended. Switching supplies tend to have radiated components that may be coupled into the ADCs. The AD10678 features separate analog and digital supply and ground currents, helping to minimize digital corruption of sensitive analog signals. The +3.3VE supply provides power to the clock distribution circuit. The +3.3VD supply provides power to the digital output section of the ADCs, the PECL-to-TTL translator, and the CPLD. Separate +3.3VE and +3.3VD supplies are used to prevent modulation of the clock signal with digital noise. The +5VA supply provides power to the analog sections of the ADCs. Decoupling capacitors are strategically placed throughout the circuit to provide low impedance noise shunts to ground. The +5VA supply (analog power) should be decoupled to AGND (analog ground) and +3.3VD (digital power) should be decoupled to DGND (digital ground). The +3.3VE supply (analog power) should be decoupled to AGND. The evaluation board schematic and layout data provide a typical PCB implementation of the AD10678.
the reference. Since AIN and AIN are 180 degrees out of phase, the differential analog input signal is 2.15 V p-p. The analog input is designed for a 50 input impedance for easy interface to commercially available cables, filters, and drivers, etc. The AD10678 encode inputs are ac-coupled to a PECL differential receiver/driver. The output of the receiver/driver provides a clock source for a 1:5 PECL clock driver and a PECL-to-TTL translator. The 1:5 PECL clock driver provides the differential encode signal for each of the four high speed analog-to-digital converters. The PECL-to-TTL translator is used to provide a clock source for the complex programmable logic device (CPLD). The digital outputs from the four ADCs drive 120 series output terminators and are applied to the CPLD for postprocessing. The digital outputs are added together in the complex programmable logic device through a ripple-carry adder, which provides the 16-bit data output. The AD10678 provides valid data following 10 pipeline delays. The result is a 16-bit parallel digital CMOS compatible word coded as true binary.
Analog and Digital Grounding
Although the AD10678 provides separate analog and digital ground pins, the device should be treated as an analog component. Proper grounding is essential in high speed, high resolution systems. Multilayer printed circuit boards are recommended to provide optimal grounding and power distribution. The use of power and ground planes provides distinct advantages. Power and ground planes minimize the loop area encompassed by a signal and its return path, minimize the impedance associated with power and ground paths, and provide a distributed capacitor formed by the power plane, printed circuit board material, and ground plane. The AD10678 unit is provided with four metal standoffs (see Figure 7). MH2 is located in the center of the unit and MH1 is located directly below analog header P3. Both of these standoffs are tied to analog ground and should be connected accordingly on the next level assembly for optimum performance. The two standoffs located near P1 and P2 (MH3 and MH4) are tied to digital ground and should be connected accordingly on the next-level assembly.
Input Stage
The user is provided with a single-to-differential transformer coupled input. The input impedance is 50 and requires a 2.15 V p-p input level to achieve full scale.
Encoding the AD10678
The AD10678 encode signal must be a high quality, low phase noise source to prevent performance degradation. The clock input must be treated as an analog input signal because aperture jitter may affect dynamic performance. For optimum performance, the AD10678 must be clocked differentially.
Output Loading
Take care when designing the data receivers for the AD10678. The complex programmable logic device 16-bit outputs drive 120 series resistors to limit the amount of current that can flow into the output stage. To minimize capacitive loading, there should only be one gate on each of the output pins. A typical CMOS gate combined with the PCB trace has a load of approximately 10 pF. It should be noted that extra capacitive loading increases output timing and invalidates timing specifications. Digital output timing is guaranteed with a 10 pF load.
Rev. A | Page 13 of 20
AD10678
Other Notes
The circuit is configured on a 2.2" x 2.8" laminate board with three sets of connector interface pads. The pads are configured in such a way that easy "keying" is provided to the user. The pads are made for low profile applications and have a total height of 0.12" after mating. The part numbers for the header mates are provided in Figure 7. All pins of the analog and digital sections are described in Table 7 and Table 8.
Evaluation Board
The AD10678 evaluation board provides an easy way to test the 16-bit 80 MSPS A/D converter. The board requires a clock source, an analog input signal, two 3.3 V power supplies, and a 5 V power supply. The clock source is buffered on the board to provide the clock for the AD10678, a latch, and a data ready signal. To use the AD10678 data ready output to clock the buffer memory, remove R24 (0.0 ) and install a 0.0 resistor at R31 (DNI). The ADC digital outputs are latched on board by a 74LCX16374. The digital outputs and output clock are available on a 40-pin connector J1. Power is supplied to the board via uninsulated metal banana jacks. The analog input is connected via an SMA connector AIN. The analog input section provides for a single-ended input option or a differential input option. The board is shipped in a single-ended analog input option. Removing a ground tie at E17 converts the circuit to a differential analog input configuration.
Table 9. PCB Bill of Material
Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Quantity 1 1 3 3 6 2 1 1 19 1 4 17 6 4 1 1 Reference Designator J1 U1 L1 to L3 J11 to J13 P1, P2, P8 to P10, P12 U5, U6 U7 R24 R0 to R16, R20, R23 R17 R18, R19, R21, R22 C1, C10 to C13, C16 to C18, C23 to C26, C29 to C32 C8, C9, C4, C15, C27, C33 J2, J3, J5, J6 A1 AD106xx Evaluation Board Description Connector, 40-Position Header, Male Straight IC, LV 16-Bit D-Type Flip-Flop with 5 V Tolerant I/O Common-Mode Surface-Mount Ferrite Bead 20 Connector, 1 mm Single Element Interface Uninsulated BANANA JACK All Metal IC, 3.3 V/5 V ECL Differential Receiver/Driver IC, 3.3 V Dual Differential LVPECL to LVTTL Translator RES 0.0 1/10 W 5% 0805 SMD RES 51.1 1/10 W 1% 0805 SMD RES 18.2 k 1/10 W 1% 0805 SMD RES 100 1/10 W 1% 0805 SMD CAP 0.1 F 16 V CERAMIC X7R 0805 CAP 10 F 10 V CERAMIC Y5V 1206 CONNECTOR, SMA JACK 200 Mil STR GOLD ASSEMBLY, AD10678BWS GS04483 (PCB)
Rev. A | Page 14 of 20
DGND
+3.3VD
AD10678 PART OUTLINE
C33 10F 10V BUFMEM U1 +3.3VD R25 DNI DGND LATCH R30 DNI DGND C31 0.1F 16V MH4
MH1-4 = DUT MOUNTING HOLES +5VA DGND
+3.3VE DGND AGND AGND J2 ANALOG INPUT
MH2
E15
C30 0.1F 16V
C14 10F 10V
C32 0.1F 16V C15 10F 10V C11 0.1F 16V AGND C12 0.1F 16V E17 FSI-110-03-G-D-AD-TR R18 100 AGND
19 17 15 13 11 9 7 5 3 1
J11 20 20 19 19 18 18 17 17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 99 8 8 77 6 6 55 4 4 33 2 2 11 FSI-110-03-G-D-AD-TR
J1 R0 51.1 R1 51.1 R2 51.1 R3 51.1 R4 51.1 R5 51.1 R6 51.1 R7 51.1
42 31 7 18 23 22 20 19 17 16 14 13
+3.3VE
8 7 6 5
J6 ENCODE R27 DNI AGND AGND J3
C10 0.1F 16V
U5
R16 51.1
1 2 3 4
NC VCC D Q D Q VBB VEE
1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20
1 J13 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15 18 17 20 19
MC10EL16D AGND
J5 ENCODE AGND AGND DGND SINGLE-ENDED DIFFERENTIAL INPUT OPTION INPUT OPTION
19 17 15 13 11 9 7 5 3 1 20 18 16 14 12 10 8 6 4 2
C13 0.1F 16V AGND R19 100 AGND AGND DGND MH3
J12
R8 51.1 R9 51.1 R10 51.1 R11 51.1 R12 51.1 R13 51.1 R14 51.1 R15 51.1 +3.3VD
12 11 9 8 6 5 3 2 21 15 10 4
39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1
39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 E7 74LCX16374MTD
40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 40-PIN HMS E8 C1 0.1F 16V DGND DGND DGND
40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2
MH1
25 24 26 27 29 30 32 33 35 36 48 1 37 38 40 41 43 44 46 47 28 34 39 45
VCC VCC CP2 VCC OE2 VCC I15 O15 O14 I14 I13 O13 I12 O12 I11 O11 O10 I10 I9 O9 I8 O8 CP1 OE1 I7 O7 I6 O6 I5 O5 I4 O4 I3 O3 I2 O2 I1 O1 I0 O0 GND GND GND GND GND GND GND GND
R20 51.1
20 18 16 14 12 10 8 6 4 2
+3.3VD U7 R29 DNI R23 51.1 R24 0.0 R28 DNI R31 DNI DRY C17 LATCH 0.1F 16V BUFMEM
J8
1 3 5 7 9 11 13
MC100ELT23D DGND DGND BYPASS CAPACITORS
AGND AGND AGND
DGND POWER CONNECTIONS +3.3VE P8 +3.3VD P12 AGND DGND 1 3 C18 0.1F 16V C29 0.1F 16V C23 0.1F 16V C28 0.1F 16V AGND DGND DGND L3 2 4 C27 10F 10V C24 0.1F 16V +3.3VD
POWER CONNECTIONS L1 P10 1 2 +3.3VE 3 4 +3.3VE +3.3VD C9 10F 10V AGND +5VA E2 C8 10F 10V AGND C25 0.1F 16V AGND AGND AGND AGND C26 0.1F 10V C16 0.1F 16V
P1
AGND
AGND
P9
L2
OPTIONAL EVALUATION BOARD GROUND TIES E6 E10 E12 E18 E19 E21 E4 E3 E20 E22 E13 E1 E5 E9 E11
+5VA
1 3
2 4
P2
AGND
AGND
AGND
AGND
AGND
AGND
DGND
HEADER 732mm
Figure 19. Evaluation Board Schematic
SI-110-03-G-D-AD-TR
DGND
R17 U6 18.2k 1 NC VCC 2 D Q 3 D Q 4 VBB VEE DGND +3.3VD DGND
8 7 6 5
R30 DNI
1 D0 2 D0 3 D1 4
MC10EL16D
R21 R22 100 100 D1 GND
VCC 8 Q0 7 Q1 6 5
2 4 6 8 10 12 14
DRY
Rev. A | Page 15 of 20
DGND
+3.3VE
DGND
DGND
DGND
DGND
DGND DGND
AD10678
03376-A-016
AD10678
AD10678/PCP EVALUATION BOARD
Figure 20. Evaluation Board Mechanical Layout Top View
Rev. A | Page 16 of 20
03376-A-017
AD10678
Figure 21. Evaluation Board Mechanical Layout Bottom View
Rev. A | Page 17 of 20
03376-A-018
AD10678
Figure 22. Evaluation Board Top Layer Copper
Figure 23. Evaluation Board Second Layer Copper
Rev. A | Page 18 of 20
03376-A-020
03376-A-019
AD10678
Figure 24. Evaluation Board Third Layer Copper
Figure 25. Evaluation Board Bottom Layer Copper
Rev. A | Page 19 of 20
03376-A-022
03376-A-021
AD10678 OUTLINE DIMENSIONS
Dimensions shown in inches Tolerances: 0.xx = 10 mils 0.xxx = 5 mils
2.795 2.745 2.695
0.170 0.120 0.070
2.220 2.170 2.120
a
AD10678BWS LOT NUMBER DATA CODE USA
0.370 0.320 0.270
0.314 0.264 0.214
Top View
Figure 26.
ORDERING GUIDE
Model AD10678BWS AD10678/PCB Temperature Range 0C to 70C 25C Package Description Non-Herm Hybrid Surf Mount (2.2" x 2.8") Evaluation Board Package Option WS-120
(c) 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03376-0-12/03(A)
Rev. A | Page 20 of 20

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